The present invention relates to a redundant memory cell selecting circuit which is designed for a defective memory cell group in a plurality of memory cell groups formed at the points of intersection of word lines and bit lines thereby forming a grid, and is relieved by being replaced with a redundant memory cell group having been previously prepared and connected to a redundant word line group.
Recent trends in the semiconductor memory device (hereinafter referred to as "memory device") industry is emphasizing greater memory device capacity, and as a result, the memory cell groups are arranged in a more integrated manner having higher density. This may cause memory cell groups to become defective in the course of the producing these memory devices. It is a common practice that such defective memory cell groups are replaced with previously prepared redundant memory cell groups by a redundant memory cell selecting circuit. This technique is essential in order to improve the yield.
Therefore, it is important to design a redundant memory cell selecting circuit, previously containing redundant memory cell groups, having numbers which are sufficient to effectively relieve memory cell groups which become defective in the course of their production.
Further, redundant memory cell selecting circuits containing a great number of redundant memory cell groups do not always operate in a normal manner. As such, the inventors of the present invention have proposed, in Japanese Patent Laid-Open Publication No. 63-206999, a redundant memory cell selecting circuit having a function of checking redundant memory cell groups for performance before the replacement of such a defective memory cell group, so as to assure that the defective memory cell group can be replaced with only a redundant memory cell group having favorable qualities.
(First Conventional Example)
The following description will discuss a first conventional redundant memory cell selecting circuit with reference to FIGS. 21 and 22.
FIG. 21 shows a first conventional redundant memory cell selecting circuit, and FIG. 22 shows a redundant-memory-cell-group selecting fuse circuit (hereinafter referred to as "selecting fuse circuit") block FB100. Each of Selecting fuse circuit blocks FB101 to FB115 has an arrangement similar to that of the selecting fuse circuit block FB100.
FIGS. 21 and 22 show: memory cell blocks MC30 to MCB7; the selecting fuse circuit blocks FB100 to FB115; redundant word line groups RWL00, RWL01, RWL10, RWL11, . . . , RWL70, and RWL71; address signals A0 to A8 and /A0 to /A8; signals SPE0, SPE1, R00, R01, R10, R11, R70, R71, /RA, and N01; fuses F00 to F11; a power voltage VCC; a grounding voltage VSS; N-channel MOS transistors QN00 to QN14; and a P-channel MOS transistor QP00.
According to the first conventional example, the redundant memory cell selecting circuit is designed whereby the defective memory cell groups among a plurality of memory cell groups formed at the points of intersection of word lines and bit lines arranged to form a grid, are replaced with redundant memory cell groups which are previously prepared and connected to redundant word line groups.
The redundant memory cell selecting circuit has eight memory cell blocks MCB0 to MCB7 designed to be selected by the logical voltages of address signals A6 to A8.
Each of the memory cell blocks has two redundant word line groups which respectively belong to first and second sets. For example, the memory cell block MCB2 has two redundant word line groups RWL20, RWL21. That is, sixteen total redundant word line groups are prepared for the eight memory cell blocks.
To select these redundant word line groups, sixteen selecting fuse circuit blocks FB100 to FB115 are respectively prepared for the sixteen redundant word line groups. For example, when it is desired to use two redundant word line groups RWL20, RWL21 of the memory cell block MCB2, fuses corresponding to the addresses of defective memory cell groups are disconnected in the selecting fuse circuit blocks FB104, FB105, so as to replace the normal word line groups connected to the defective memory cell groups with the redundant word line groups.
The following description will discuss in detail the operation of the redundant memory cell selecting circuit of the first conventional example with reference to FIG. 22. FIG. 22 shows the selecting fuse circuit block FB100. Each of the selecting fuse circuit blocks FB101 to FB115 has an arrangement similar to that of the selecting fuse circuit block FB100.
First, the logical voltage of a signal /RA becomes "Low (hereinafter referred to L)", the P-channel MOS transistor QP00 is turned on, and the logical voltage of the signal N01 becomes "High (hereinafter referred to H)". Thereafter, the logical voltage of the signal /RA becomes H, and the address signals A0 to A5, /A0 to /A5 of which logical voltages have been initially "L", are converted into address signals corresponding to the address of a defective memory cell group selected. Here, the address signals /A0 to /A5 are the logical-voltage signals of which logics are reverse to those of the address signals A0 to A5, respectively.
The address signals A0 to A5 and /A0 to /A5 are respectively supplied to the gates of twelve N-channel MOS transistors QN00 to QN11, of which half or six transistors are turned on.
At this time, when those six fuses of the fuses F100 to F111 which correspond to the address of a selected defective memory cell group are disconnected and when the memory block selecting address of the memory cell block MCB0 is selected, the logical voltage of the signal N01 becomes "H" and the logical voltage of the signal R00 becomes "L". Then, the logical voltage of the signal SPE0 becomes "H". Next, the redundant word line group RWL00 is selected by a signal of the logical multiplication of the signal SPE0 and the address signals corresponding to the memory cell block selecting address of the memory cell block MCB0.
In the redundant memory cell selecting circuit of the first conventional example having the arrangement above-mentioned, two redundant word line groups are prepared for each of the eight memory cell blocks. Accordingly, sixteen (i.e., 2.times.8) selecting fuse circuit blocks are required. Since twelve fuses are required for one selecting fuse circuit block, 192 (i.e., 12.times.16) total fuses are required.
(Second Conventional Example)
The following description will discuss the redundant memory cell selecting circuit of a second conventional example with reference to FIG. 23.
FIG. 23 shows a redundant memory cell testing circuit block 51 in the redundant memory cell selecting circuit of the second conventional example. The redundant memory cell testing circuit block is designed to check the redundant memory cell groups for performance in the redundant memory cell selecting circuit.
FIG. 23 shows: address signals A1, A2 serving as redundant memory cell selecting input signals; a control signal B; a redundant memory cell selecting output signal C; a redundant memory cell testing control signal D; redundant memory cell selecting fuses F1, and F2; P-channel MOS transistors QP1 to QP6; N-channel MOS transistors QN1 to QN7; a redundant memory cell testing circuit block 51; a selecting fuse circuit block 52; a power voltage VCC; and a grounding voltage VSS.
In the redundant memory cell selecting circuit according to the second conventional example, a normal memory cell group is selected when the logical voltage of the redundant memory cell selecting output signal C is "L", and a redundant memory cell group is selected when the logical voltage of the redundant memory cell selecting output signal C is "H".
The following description will discuss the operation of the redundant memory cell selecting circuit according to the second conventional example.
The redundant memory cell testing control signal D is floating, and the P-channel MOS transistor QP2 is turned on. Accordingly, the logical voltage of a signal entered into the gate of the N-channel MOS transistor QN3 becomes "H" to turn on the N-channel MOS transistor QN3, the logical voltage of a signal entered into the gate of the P-channel MOS transistor QP3 becomes "L" to turn off the P-channel MOS transistor QP3, and the logical voltage of a signal entered into the N-channel MOS transistor QN7 becomes "L" to turn off the N-channel MOS transistor QN7. Accordingly, a signal presenting a logical voltage identical with that of a signal at the drain of the P-channel MOS transistor QP1 serves as the redundant memory cell selecting output signal C.
First, the following will discuss the operation of the redundant memory cell selecting circuit when the fuses in the selecting fuse circuit block 52 are disconnected.
When the logical voltage of the control signal B is made "L" as the initial state, the P-channel MOS transistor QP1 is turned on, so that the logical voltage of a signal at the drain of the P-channel MOS transistor QP1 becomes "H". Then, the logical voltage of an address signal selected from the address signals A1, A2 becomes "H".
When the fuses corresponding to a selected address signal are not disconnected under the circumstances mentioned above, the logical voltage of the signal at the drain of the P-channel MOS transistor QP1 becomes "L" and the logical voltage of the redundant memory cell selecting output signal C becomes "L". Accordingly, a memory cell-group is selected.
On the other hand, if the fuses corresponding to a selected address signal are disconnected, the logical voltage of the signal at the drain of the P-channel MOS transistor QP1 becomes "H", and the logical voltage of the redundant memory cell selecting output signal C becomes "H". Accordingly, a redundant memory cell group is selected.
Thus, it is possible to select either a memory cell group or a redundant memory cell group according to the address signal selected.
The following description will discuss the operation of the redundant memory cell selecting circuit for selecting a redundant memory cell group without the fuses in the selecting fuse circuit block 52 disconnected.
The logical voltage of the redundant memory cell testing control signal D is made "L". Next, if the logical voltage of a signal entered into the gate of the N-channel MOS transistor QN3 becomes "L" to turn off the N-channel MOS transistor QN3, then the logical voltage of a signal entered into the gate of the P-channel MOS transistor QP3 becomes "H" to turn off the P-channel MOS transistor QP3, and the logical voltage of a signal entered into the date of the N-channel MOS transistor QN7 becomes "H" to turn on the N-channel MOS transistor QN7. Accordingly, the logical voltage of the redundant memory cell selecting output signal C is always "H". Thus, a redundant memory cell group is selected regardless of whether either address signal A1 or A2 is selected or whether the fuses F1, F2 are connected or disconnected.
In the redundant memory cell selecting circuit of the second conventional example having the above-mentioned arrangement, by setting the logical voltage of the redundant memory cell testing control signal D to "L", a redundant memory cell group can be selected and checked for normal operation without causing the fuses of the selecting fuse circuit block to be disconnected. In fact, an external control terminal is disposed for the redundant memory cell testing control signal D, and the redundant memory cell groups are checked with the use of this external control terminal at the time of a probe test conducted before assembling a memory device.
However, the redundant memory cell selecting circuits of the first and second conventional examples present the following problems.
With regards to the redundant memory cell selecting circuit, according to the first conventional example, a great number of redundant word line groups and a great number of selecting fuse circuit blocks are required for the memory cell blocks. Accordingly, the memory device requires a large layout area, thus increasing the area of the memory device in its entirety. This results in an increase in production costs.
To select one redundant memory cell selecting output signal C, in the redundant memory cell selecting circuit according to the second conventional example, one redundant memory cell testing control signal D is required. Accordingly, an increase in the number of redundant memory cell groups will increase the number of the redundant memory cell testing control signals D for selecting the redundant memory cell groups. When external control terminals are disposed for the redundant memory cell testing control signals D and the redundant memory cell groups are to be checked with the use of the external control terminals while a probe test is conducted before assembling a memory device, the number of the external control terminals is increased so as to increase the memory device in the chip area. Consequently, the cost of producing the memory devices will be increased. Further, a probe testing device is required to have a great number of control terminals for controlling the external control terminals, resulting in the increase in cost of the probe testing device.